1. Field of the Invention
This invention relates to a vertical power transistor device for use in an integrated circuit. More particularly, it relates to such a vertical power transistor device which has sufficient current and voltage capability to provide output power from an integrated circuit which includes low power transistors.
2. Description of the Prior Art
DMOS power transistors are known in the art, for example, as described in U.S. Pat. No. 4,345,265, issued Aug. 17, 1982 to Blanchard. Integrated circuits containing low voltage logic transistors and one or more high power DMOS transistors have been fabricated with a variety of techniques. Two of these techniques are known as self isolated and junction isolated DCMOS. These technologies both use CMOS transistors in the logic/control section of the integrated circuit, while the output transistor or transistors are DMOS. Both of these technologies have advantages for certain applications. However, the parallel sum of the output resistance of the power DMOS transistors is too large for many applications It would be advantageous to provide a power transistor structure which did not result in such a large output resistance.